抄録
Novel device architecture is presented, where surface channel (SC) pMOSFET and buried channel (BC) pMOSFET are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by BC structure for I/O and analog circuits, and high-speed and high integration are realized by SC structure for core circuits in System-on-a Chip (SoC).
本文言語 | English |
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ページ(範囲) | 869-872 |
ページ数 | 4 |
ジャーナル | Technical Digest - International Electron Devices Meeting |
出版ステータス | Published - 2001 12 1 |
外部発表 | はい |
イベント | IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States 継続期間: 2001 12 2 → 2001 12 5 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry