TY - JOUR
T1 - SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures
AU - Nishida, Y.
AU - Sayama, H.
AU - Ohta, K.
AU - Oda, H.
AU - Katayama, M.
AU - Inoue, Y.
AU - Morimoto, H.
AU - Inuishi, M.
PY - 2001/12/1
Y1 - 2001/12/1
N2 - Novel device architecture is presented, where surface channel (SC) pMOSFET and buried channel (BC) pMOSFET are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by BC structure for I/O and analog circuits, and high-speed and high integration are realized by SC structure for core circuits in System-on-a Chip (SoC).
AB - Novel device architecture is presented, where surface channel (SC) pMOSFET and buried channel (BC) pMOSFET are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by BC structure for I/O and analog circuits, and high-speed and high integration are realized by SC structure for core circuits in System-on-a Chip (SoC).
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M3 - Conference article
AN - SCOPUS:0035714856
SP - 869
EP - 872
JO - Technical Digest - International Electron Devices Meeting
JF - Technical Digest - International Electron Devices Meeting
SN - 0163-1918
T2 - IEEE International Electron Devices Meeting IEDM 2001
Y2 - 2 December 2001 through 5 December 2001
ER -