SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures

Y. Nishida, H. Sayama, K. Ohta, H. Oda, M. Katayama, Y. Inoue, H. Morimoto, M. Inuishi

研究成果: Conference article査読

5 被引用数 (Scopus)

抄録

Novel device architecture is presented, where surface channel (SC) pMOSFET and buried channel (BC) pMOSFET are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by BC structure for I/O and analog circuits, and high-speed and high integration are realized by SC structure for core circuits in System-on-a Chip (SoC).

本文言語English
ページ(範囲)869-872
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 2001 12 1
外部発表はい
イベントIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
継続期間: 2001 12 22001 12 5

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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