Soft error tolerant latch designs with low power consumption (invited paper)

    研究成果: Conference contribution

    2 引用 (Scopus)

    抜粋

    As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before. Unlike traditional hard-errors caused by permanent physical damage which can't be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors. However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs. For this reason, soft error tolerant design techniques have gained great research interest. In this paper, we will explain the soft error mechanism and then review the existing soft error tolerant design techniques with particular emphasis on SEH family because they can achieve low power consumption and small performance overhead as well.

    元の言語English
    ホスト出版物のタイトルProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
    出版者IEEE Computer Society
    ページ52-55
    ページ数4
    2017-October
    ISBN(電子版)9781509066247
    DOI
    出版物ステータスPublished - 2018 1 8
    イベント12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
    継続期間: 2017 10 252017 10 28

    Other

    Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
    China
    Guiyang
    期間17/10/2517/10/28

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • これを引用

    Tajima, S., Togawa, N., Yanagisawa, M., & Shi, Y. (2018). Soft error tolerant latch designs with low power consumption (invited paper). : Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (巻 2017-October, pp. 52-55). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252409