Soft error tolerant latch designs with low power consumption (invited paper)

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before. Unlike traditional hard-errors caused by permanent physical damage which can't be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors. However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs. For this reason, soft error tolerant design techniques have gained great research interest. In this paper, we will explain the soft error mechanism and then review the existing soft error tolerant design techniques with particular emphasis on SEH family because they can achieve low power consumption and small performance overhead as well.

本文言語English
ホスト出版物のタイトルProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
編集者Yajie Qin, Zhiliang Hong, Ting-Ao Tang
出版社IEEE Computer Society
ページ52-55
ページ数4
ISBN(電子版)9781509066247
DOI
出版ステータスPublished - 2017 7 1
イベント12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
継続期間: 2017 10 252017 10 28

出版物シリーズ

名前Proceedings of International Conference on ASIC
2017-October
ISSN(印刷版)2162-7541
ISSN(電子版)2162-755X

Other

Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
CountryChina
CityGuiyang
Period17/10/2517/10/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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