Software-cooperative power-efficient heterogeneous multi-core for media processing

Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

研究成果: Conference contribution

7 引用 (Scopus)

抜粋

A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.

元の言語English
ホスト出版物のタイトル2008 Asia and South Pacific Design Automation Conference, ASP-DAC
ページ736-741
ページ数6
DOI
出版物ステータスPublished - 2008 8 21
イベント2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
継続期間: 2008 3 212008 3 24

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Korea, Republic of
Seoul
期間08/3/2108/3/24

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • これを引用

    Shikano, H., Ito, M., Uchiyama, K., Odaka, T., Hayashi, A., Masuura, T., Mase, M., Shirako, J., Wada, Y., Kimura, K., & Kasahara, H. (2008). Software-cooperative power-efficient heterogeneous multi-core for media processing. : 2008 Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 736-741). [4484049] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2008.4484049