SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Katsuhiro Suma*, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutami Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara

*この研究の対応する著者

研究成果: Article査読

27 被引用数 (Scopus)

抄録

An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc = 3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80 °C is longer than 20 s (Vcc = 3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's.

本文言語English
ページ(範囲)1323-1329
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
29
11
DOI
出版ステータスPublished - 1994 11
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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