Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder

Yiqing Huang, Qin Liu, Takeshi Ikenaga

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

In this paper, we contribute one reconfigurable integer motion estimation (IME) architectures (namely RPPSAD) based on adaptive algorithm. Firstly, based on the pixel difference analysis, the spatial redundancy is further exploited and three subsampling patterns are selected adaptively for the IME process. Secondly, in order to achieve data reuse and power reduction in memory part, the reference pixels in search window are reorganization into two memory groups, which output pixel data interactively for adaptive subsampling. Moreover, a compressor tree based circuit level optimization is included in our design to reduce hardware cost. Synthesized with TSMC 0.18um technology, averagely 10k gates hardware can be reduced for the whole IME engine based on our optimization. With 481k gates at 110.5MHz, one 720-p, 30-fps HDTV integer motion estimation engine is designed. Compared with previous work, our design can achieve 39.8% reduction in power consumption with only 3.44% increase in hardware.

本文言語English
ホスト出版物のタイトルDSP 2009:16th International Conference on Digital Signal Processing, Proceedings
DOI
出版ステータスPublished - 2009 11 20
イベントDSP 2009:16th International Conference on Digital Signal Processing - Santorini, Greece
継続期間: 2009 7 52009 7 7

出版物シリーズ

名前DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings

Conference

ConferenceDSP 2009:16th International Conference on Digital Signal Processing
国/地域Greece
CitySantorini
Period09/7/509/7/7

ASJC Scopus subject areas

  • コンピュータ ビジョンおよびパターン認識
  • 信号処理

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