Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8%~35.4% reduction in area and 11.8%~27.9% in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.

本文言語English
ホスト出版物のタイトル2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728103976
DOI
出版ステータスPublished - 2019 1 1
イベント2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
継続期間: 2019 5 262019 5 29

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
2019-May
ISSN(印刷版)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
CountryJapan
CitySapporo
Period19/5/2619/5/29

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント 「Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル