Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Nozomu Togawa*, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

*この研究の対応する著者

研究成果: Conference article査読

抄録

In this paper, we propose a sub-operation parallelism optimization algorithm in SIMD processor synthesis. Given an initial assembly code and timing constraints, our algorithm synthesizes a processor core with sub-operation parallelism optimization for SIMD functional units. First we consider an initial processor which has sufficient hardware units for executing an initial assembly code. An initial processor core includes the maximum sub-operation parallelism for each SIMD functional unit. By gradually reducing sub-operation parallelism, we can finally have a processor core with small area meeting a given timing constraints. We show the effectiveness of our proposed algorithm through experimental results.

本文言語English
論文番号1465383
ページ(範囲)3499-3502
ページ数4
ジャーナルProceedings - IEEE International Symposium on Circuits and Systems
DOI
出版ステータスPublished - 2005
イベントIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
継続期間: 2005 5 232005 5 26

ASJC Scopus subject areas

  • 電子工学および電気工学

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