Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2nm

T. Kuroi, S. Shimizu, S. Ogino, A. Teramoto, M. Shirahata, Y. Okumura, M. Inuishi, H. Miyoshi

研究成果: Conference article査読

11 被引用数 (Scopus)

抄録

The high performance 0.25 μm dual gate CMOS with ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic application. The boron penetration can effectively be suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. Moreover the inverter delay with the Al interconnect load can be remarkably improved by the highly drivable MOSFETs with thin gate oxide for low-voltage operation. Furthermore the hot carrier degradation of NMOSFETs can be suppressed as reducing the oxide thickness. However it is found that the hot-carrier degradation of PMOSFETs is enhanced in thin-oxide region under channel hot-hole injection.

本文言語English
ページ(範囲)210-211
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 1996 1 1
外部発表はい
イベントProceedings of the 1996 Symposium on VLSI Technology - Honolulu, HI, USA
継続期間: 1996 6 111996 6 13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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