@article{831362f0ece540f2a6f8ec3fdb284acb,
title = "Supplemental PDK for ASAP7 using synopsys flow",
abstract = "This paper reports a supplemental process design kit (PDK) for ASAP7 PDK using Synopsys design flow. ASAP7 is a PDK for “predictable” 7-nm FinFET technology node. ASAP7 PDK is useful for academical and educational purpose, however it only supports Cadence platform for Place and Route. A supplemental PDK is designed for ASAP7 to use Synopsys platform for Place and Route. This PDK is opened at the author{\textquoteright}s GitHub site for both acamemical and educational usage.",
keywords = "Process design kit, ASAP7",
author = "Shinichi Nishizawa and Lin, {Shih Ting} and Li, {Yih Lang} and Hidetoshi Onodera",
note = "Funding Information: Acknowledgments Authors thank all of contributers for ASAP7 PDK design and distribution. This work is also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Mentor Graphics, Inc. Publisher Copyright: c 2021 Information Processing Society of Japan",
year = "2021",
doi = "10.2197/IPSJTSLDM.14.24",
language = "English",
volume = "14",
pages = "24--26",
journal = "IPSJ Transactions on System LSI Design Methodology",
issn = "1882-6687",
publisher = "Information Processing Society of Japan",
}