Suppression of boron penetration from source/drain-extension to improve gate leakage characteristics and gate-oxide reliability for 65-nm node CMOS and beyond

Takashi Hayashi, Tomohiro Yamashita, Katsuya Shiga, Kiyoshi Hayashi, Hidekazu Oda, Takahisa Eimori, Masahide Inuishi, Yuzuru Ohji

研究成果: Article査読

抄録

Boron penetration from the poly-silicon gate to the silicon substrate through gate dielectrics is a crucial problem in the dual gate complementary metal-oxide semiconductor (CMOS) process. Therefore, the plasma nitridation technique has been studied well, and it has succeeded to suppress boron penetration. However, boron penetration occurs not only from the doped poly-silicon gate but also from the substrate, and resulting in several degradations of gate-oxide characteristics. On the other hand, the boron concentration of source/drain (S/D) extension has been increasing with gate shrinkage. We found that boron penetration from the S/D extension becomes a crucial problem in gate leakage and gate-oxide integrity, particularly for nanoscale positive-channel MOS (pMOS). In this study, we examined several treatments in detail to suppress boron penetration from the S/D extension, and demonstrated that the plasma nitridation treatment after gate etching is the best solution for 65-nm node CMOS and beyond.

本文言語English
ページ(範囲)2157-2160
ページ数4
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
44
4 B
DOI
出版ステータスPublished - 2005 4
外部発表はい

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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