Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

H. Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.

本文言語English
ホスト出版物のタイトル2013 IEEE International Electron Devices Meeting, IEDM 2013
ページ33.2.1-33.2.4
DOI
出版ステータスPublished - 2013 12 1
外部発表はい
イベント2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
継続期間: 2013 12 92013 12 11

出版物シリーズ

名前Technical Digest - International Electron Devices Meeting, IEDM
ISSN(印刷版)0163-1918

Other

Other2013 IEEE International Electron Devices Meeting, IEDM 2013
CountryUnited States
CityWashington, DC
Period13/12/913/12/11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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