Suspicious timing error prediction with in-cycle clock gating

研究成果: Conference contribution

17 被引用数 (Scopus)

抄録

Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees 'always correct' operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with 'always correct' outputs.

本文言語English
ホスト出版物のタイトルProceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
ページ335-340
ページ数6
DOI
出版ステータスPublished - 2013 7 5
イベント14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA, United States
継続期間: 2013 3 42013 3 6

出版物シリーズ

名前Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN(印刷版)1948-3287
ISSN(電子版)1948-3295

Conference

Conference14th International Symposium on Quality Electronic Design, ISQED 2013
国/地域United States
CitySanta Clara, CA
Period13/3/413/3/6

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

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