Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto

    研究成果: Conference contribution

    15 被引用数 (Scopus)

    抄録

    The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

    本文言語English
    ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    ページ772-775
    ページ数4
    DOI
    出版ステータスPublished - 2008
    イベント2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul
    継続期間: 2008 3 212008 3 24

    Other

    Other2008 Asia and South Pacific Design Automation Conference, ASP-DAC
    CitySeoul
    Period08/3/2108/3/24

    ASJC Scopus subject areas

    • 工学(全般)

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