We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bitline access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 μm2 8T-DP-cell for which the cell size is only 1.44× larger than a 6T-single-port (SP)-cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2 , which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.
ASJC Scopus subject areas
- Electrical and Electronic Engineering