Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access

Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara

研究成果: Article

39 引用 (Scopus)

抄録

We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bitline access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 μm2 8T-DP-cell for which the cell size is only 1.44× larger than a 6T-single-port (SP)-cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2 , which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

元の言語English
記事番号4787570
ページ(範囲)977-986
ページ数10
ジャーナルIEEE Journal of Solid-State Circuits
44
発行部数3
DOI
出版物ステータスPublished - 2009 3
外部発表Yes

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Static random access storage
Macros
Random access storage
Transistors
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access. / Nii, Koji; Tsukamoto, Yasumasa; Yabuuchi, Makoto; Masuda, Yasuhiro; Imaoka, Susumu; Usui, Keiichi; Ohbayashi, Shigeki; Makino, Hiroshi; Shinohara, Hirofumi.

:: IEEE Journal of Solid-State Circuits, 巻 44, 番号 3, 4787570, 03.2009, p. 977-986.

研究成果: Article

Nii, K, Tsukamoto, Y, Yabuuchi, M, Masuda, Y, Imaoka, S, Usui, K, Ohbayashi, S, Makino, H & Shinohara, H 2009, 'Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access', IEEE Journal of Solid-State Circuits, 巻. 44, 番号 3, 4787570, pp. 977-986. https://doi.org/10.1109/JSSC.2009.2013766
Nii, Koji ; Tsukamoto, Yasumasa ; Yabuuchi, Makoto ; Masuda, Yasuhiro ; Imaoka, Susumu ; Usui, Keiichi ; Ohbayashi, Shigeki ; Makino, Hiroshi ; Shinohara, Hirofumi. / Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access. :: IEEE Journal of Solid-State Circuits. 2009 ; 巻 44, 番号 3. pp. 977-986.
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AU - Masuda, Yasuhiro

AU - Imaoka, Susumu

AU - Usui, Keiichi

AU - Ohbayashi, Shigeki

AU - Makino, Hiroshi

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KW - 65 nm

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KW - Dual-port

KW - Embedded SRAM

KW - High density

KW - Low power

KW - Low voltage

KW - Memory

KW - Stability

KW - Two-port

KW - Variability

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