Synthesis of parallel prefix adders considering switching activities

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

研究成果: Conference contribution

1 引用 (Scopus)

抄録

This paper addresses parallel prefix adder synthesis which targets minimization of the total switching activities under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization has been proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restriction on the subset. This approach can be applied for switching cost minimization almost directly, though it is not so effective as area minimization in some cases. In this paper, a heuristic is proposed which estimates the effect of the restructuring phase and improve cost calculation fo some specific cases. Through various kinds of experiments, conditions where this approach can be executed effectively is also discussed. & copy; 2008 IEEE.

元の言語English
ホスト出版物のタイトル26th IEEE International Conference on Computer Design 2008, ICCD
ページ404-409
ページ数6
DOI
出版物ステータスPublished - 2008
イベント26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA
継続期間: 2008 10 122008 10 15

Other

Other26th IEEE International Conference on Computer Design 2008, ICCD
Lake Tahoe, CA
期間08/10/1208/10/15

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Adders
Thermodynamic properties
Dynamic programming
Costs
Experiments

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Matsunaga, T., Kimura, S., & Matsunaga, Y. (2008). Synthesis of parallel prefix adders considering switching activities. : 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 404-409). [4751892] https://doi.org/10.1109/ICCD.2008.4751892

Synthesis of parallel prefix adders considering switching activities. / Matsunaga, Taeko; Kimura, Shinji; Matsunaga, Yusuke.

26th IEEE International Conference on Computer Design 2008, ICCD. 2008. p. 404-409 4751892.

研究成果: Conference contribution

Matsunaga, T, Kimura, S & Matsunaga, Y 2008, Synthesis of parallel prefix adders considering switching activities. : 26th IEEE International Conference on Computer Design 2008, ICCD., 4751892, pp. 404-409, 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, 08/10/12. https://doi.org/10.1109/ICCD.2008.4751892
Matsunaga T, Kimura S, Matsunaga Y. Synthesis of parallel prefix adders considering switching activities. : 26th IEEE International Conference on Computer Design 2008, ICCD. 2008. p. 404-409. 4751892 https://doi.org/10.1109/ICCD.2008.4751892
Matsunaga, Taeko ; Kimura, Shinji ; Matsunaga, Yusuke. / Synthesis of parallel prefix adders considering switching activities. 26th IEEE International Conference on Computer Design 2008, ICCD. 2008. pp. 404-409
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