Synthesis of parallel prefix adders considering switching activities

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

This paper addresses parallel prefix adder synthesis which targets minimization of the total switching activities under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization has been proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restriction on the subset. This approach can be applied for switching cost minimization almost directly, though it is not so effective as area minimization in some cases. In this paper, a heuristic is proposed which estimates the effect of the restructuring phase and improve cost calculation fo some specific cases. Through various kinds of experiments, conditions where this approach can be executed effectively is also discussed. & copy; 2008 IEEE.

本文言語English
ホスト出版物のタイトル26th IEEE International Conference on Computer Design 2008, ICCD
ページ404-409
ページ数6
DOI
出版ステータスPublished - 2008 12 1
イベント26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States
継続期間: 2008 10 122008 10 15

出版物シリーズ

名前26th IEEE International Conference on Computer Design 2008, ICCD

Conference

Conference26th IEEE International Conference on Computer Design 2008, ICCD
国/地域United States
CityLake Tahoe, CA
Period08/10/1208/10/15

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「Synthesis of parallel prefix adders considering switching activities」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル