Temperature compensated piezoresistor fabricated by high energy ion implantation

Takahiro Nishimoto*, Shuichi Shoji, Kazuyuki Minami, Masayoshi Esashi

*この研究の対応する著者

研究成果: Article査読

2 被引用数 (Scopus)

抄録

We developed piezoresistors with an intrinsic compensation of the offset temperature characteristics. High energy ion implantation was applied to fabricate this type of piezoresistor [1]. The dopant profile of the buried piezoresistor resembles to that of the junction gate field effect transistor (JFET). The buried layer corresponds to a channel of JFET, and the substrate bias corresponds to the gate voltage. Owing to the independent temperature varying parameters, i.e., width of the depletion layer and carrier mobility in the channel, the drain current of the JFET has a temperature independent point at an appropriate gate source voltage. The effect was used in the new type of buried piezoresistor which has a driving point of zero temperature coefficient of resistance at an appropriate gate source voltage.

本文言語English
ページ(範囲)152-156
ページ数5
ジャーナルIEICE Transactions on Electronics
E78-C
2
出版ステータスPublished - 1995 2 1
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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