Test data compression of 100x for scan-based BIST

Masayuki Arai*, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

*この研究の対応する著者

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

本文言語English
ホスト出版物のタイトル2006 IEEE International Test Conference, ITC
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(印刷版)1424402921, 9781424402922
DOI
出版ステータスPublished - 2006
外部発表はい
イベント2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
継続期間: 2006 10月 222006 10月 27

出版物シリーズ

名前Proceedings - International Test Conference
ISSN(印刷版)1089-3539

Conference

Conference2006 IEEE International Test Conference, ITC
国/地域United States
CitySanta Clara, CA
Period06/10/2206/10/27

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 応用数学

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