The switching glitch power leakage model

Hongying Liu*, Guoyu Qian, Yukiyasu Tsunoo, Satoshi Goto

*この研究の対応する著者

研究成果査読

4 被引用数 (Scopus)

抄録

Power analysis attacks are based on analyzing the power consumption of the cryptographic devices while they perform the encryption operation. Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. It has been one of the effective side channel attacks that threaten the security of CMOS circuits. However, few works consider the leakage of glitches at the logic gates. In this paper, we present a new power consumption model, namely Switching Glitch (SG) power leakage model, which not only considers the data dependent switching activities but also including glitch power consumptions in CMOS circuits. Additionally, from a theoretical point of view, we show how to estimate the glitch factor. The experiments against AES implementation validate the proposed model. Compared with CPA based on Hamming Distance model, the power traces of recovering keys have been decreased by as much as 28.9%.

本文言語English
ページ(範囲)1787-1794
ページ数8
ジャーナルJournal of Software
6
9
DOI
出版ステータスPublished - 2011

ASJC Scopus subject areas

  • ソフトウェア
  • 人工知能
  • 人間とコンピュータの相互作用

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