THREE DIMENSIONAL LEAKAGE CURRENT IN CORRUGATED CAPACITOR CELLS.

Eiji Takeda*, Kan Takeuchi, Atsushi Hiraiwa, Toru Toyabe, Hideo Sunami, Kiyoo Itoh

*この研究の対応する著者

研究成果: Conference contribution

抄録

The mechanism of three-dimensional leakage current in a corrugated capacitor cell for megabit DRAMs has been clarified both experimentally and theoretically using a 3-D device simulator (CADDETH). This study shows that this current is almost completely defined by using the minimum value of the potential barrier height between cells. This is the case even if there is a complicated potential form due to three-dimensional effects and/or sophisticated device structures. Furthermore, the three-dimensional effects in the leakage current caused by back bias penetration are discussed in detail. On the basis of these results, significant guidelines are proposed for trench capacitor cells.

本文言語English
ホスト出版物のタイトルConference on Solid State Devices and Materials
Place of PublicationTokyo, Jpn
出版社Japan Soc of Applied Physics
ページ37-40
ページ数4
ISBN(印刷版)4930813107
出版ステータスPublished - 1985
外部発表はい

ASJC Scopus subject areas

  • 工学(全般)

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