抄録
The mechanism of three-dimensional leakage current in a corrugated capacitor cell for megabit DRAMs has been clarified both experimentally and theoretically using a 3-D device simulator (CADDETH). This study shows that this current is almost completely defined by using the minimum value of the potential barrier height between cells. This is the case even if there is a complicated potential form due to three-dimensional effects and/or sophisticated device structures. Furthermore, the three-dimensional effects in the leakage current caused by back bias penetration are discussed in detail. On the basis of these results, significant guidelines are proposed for trench capacitor cells.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Conference on Solid State Devices and Materials |
| Place of Publication | Tokyo, Jpn |
| 出版社 | Japan Soc of Applied Physics |
| ページ | 37-40 |
| ページ数 | 4 |
| ISBN（印刷版） | 4930813107 |
| 出版ステータス | Published - 1985 |
| 外部発表 | はい |
ASJC Scopus subject areas
- Engineering(all)