Throughput driven check point selection in suspicious timing error prediction based designs

    研究成果: Conference contribution

    抄録

    In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection will affect both the maximal operation frequency and the suspicious timing error overestimation rate, both of which have an effect on the overall throughput, thus an analysis on the check point selection is also given. In our work, the circuit can be overclocked by a factor of 2 or more with ignorable area overhead while guarantees the always-correct output.

    元の言語English
    ホスト出版物のタイトル2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
    出版者IEEE Computer Society
    ISBN(印刷物)9781479925070
    DOI
    出版物ステータスPublished - 2014
    イベント2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Santiago
    継続期間: 2014 2 252014 2 28

    Other

    Other2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
    Santiago
    期間14/2/2514/2/28

    Fingerprint

    Throughput
    Networks (circuits)

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    これを引用

    Igarashi, H., Shi, Y., Yanagisawa, M., & Togawa, N. (2014). Throughput driven check point selection in suspicious timing error prediction based designs. : 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings [6820280] IEEE Computer Society. https://doi.org/10.1109/LASCAS.2014.6820280

    Throughput driven check point selection in suspicious timing error prediction based designs. / Igarashi, Hiroaki; Shi, Youhua; Yanagisawa, Masao; Togawa, Nozomu.

    2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 2014. 6820280.

    研究成果: Conference contribution

    Igarashi, H, Shi, Y, Yanagisawa, M & Togawa, N 2014, Throughput driven check point selection in suspicious timing error prediction based designs. : 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings., 6820280, IEEE Computer Society, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, 14/2/25. https://doi.org/10.1109/LASCAS.2014.6820280
    Igarashi H, Shi Y, Yanagisawa M, Togawa N. Throughput driven check point selection in suspicious timing error prediction based designs. : 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society. 2014. 6820280 https://doi.org/10.1109/LASCAS.2014.6820280
    Igarashi, Hiroaki ; Shi, Youhua ; Yanagisawa, Masao ; Togawa, Nozomu. / Throughput driven check point selection in suspicious timing error prediction based designs. 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 2014.
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