Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering

Fan Yang, Minghao Lin, Heming Sun, Shinji Kimura

研究成果: Conference contribution

抄録

3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSVges. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.

本文言語English
ホスト出版物のタイトル2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1200-1203
ページ数4
2017-August
ISBN(電子版)9781509063895
DOI
出版ステータスPublished - 2017 9 27
イベント60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States
継続期間: 2017 8 62017 8 9

Other

Other60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
国/地域United States
CityBoston
Period17/8/617/8/9

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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