Timing verification of sequential logic circuits based on controlled multi-clock path analysis

Kazuhiro Nakamura, Shinji Kimura, Kazuyoshi Takagi, Katsumasa Watanabe

研究成果: Article

2 被引用数 (Scopus)

抄録

This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

本文言語English
ページ(範囲)2515-2520
ページ数6
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E81-A
12
出版ステータスPublished - 1998 1 1
外部発表はい

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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