As technology scaling, three-dimensional integrated circuits (3D-ICs) are emerging as a promising solution to address the challenges in system on chips (SoCs). Moreover, it's a necessity to design an efficient Network-on-Chip (NoC) topology for the interconnection issues of 3D SoCs. In this paper, we propose a topology-aware floorplanning method to determine the power-performance efficient 3D NoC topology. Unlike the previous works which explore the path allocation of the NoC components and Through-Silicon Vias (TSVs) assignment after the floorplan of cores is fixed, we integrate these steps (the clustering of cores + the placement of cores and switches + the path allocation + the TSV-aware topology evaluation) within the 3D floorplanning procedure. Experimental results show the effectiveness of our method.
|ホスト出版物のタイトル||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版ステータス||Published - 2013|
|イベント||2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing|
継続期間: 2013 5月 19 → 2013 5月 23
|Other||2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013|
|Period||13/5/19 → 13/5/23|
ASJC Scopus subject areas