Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis

Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

As technology scaling, three-dimensional integrated circuits (3D-ICs) are emerging as a promising solution to address the challenges in system on chips (SoCs). Moreover, it's a necessity to design an efficient Network-on-Chip (NoC) topology for the interconnection issues of 3D SoCs. In this paper, we propose a topology-aware floorplanning method to determine the power-performance efficient 3D NoC topology. Unlike the previous works which explore the path allocation of the NoC components and Through-Silicon Vias (TSVs) assignment after the floorplan of cores is fixed, we integrate these steps (the clustering of cores + the placement of cores and switches + the path allocation + the TSV-aware topology evaluation) within the 3D floorplanning procedure. Experimental results show the effectiveness of our method.

元の言語English
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
ページ1732-1735
ページ数4
DOI
出版物ステータスPublished - 2013
イベント2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing
継続期間: 2013 5 192013 5 23

Other

Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Beijing
期間13/5/1913/5/23

    フィンガープリント

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Huang, B., Chen, S., Zhong, W., & Yoshimura, T. (2013). Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis. : Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1732-1735). [6572199] https://doi.org/10.1109/ISCAS.2013.6572199