Topology-Optimization-based conductor pattern design for inductance cancellation structure to reduce common- and differential-mode noise

Katsuya Nomura, Atsuhiro Takahashi, Takashi Kojima, Shintaro Yamasaki, Kentaro Yaji, Hiroki Bo, Kikuo Fujita

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Topology optimization, a simulation-based optimization technique to mathematically derive an optimal structure, is applied to the conductor design of an inductance cancellation structure to reduce common-and differential-mode noise. The design of an appropriate conductor pattern for an inductance cancellation structure is difficult due to the unintentional magnetic couplings between the multiple loops mounted to cancel the parasitic inductances of X and Y capacitors. In topology optimization, this design problem is formulated as an optimization problem and an optimal structure is obtained by repeated modification of the conductor pattern using mathematical programming. The performance of circuit boards before and after optimization is evaluated using mixed-mode s-parameters. Both simulation and experimental measurement verify that the effect of inductance cancellation is improved by this optimization.

本文言語English
ホスト出版物のタイトル34th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ページ2900-2905
ページ数6
ISBN(電子版)9781538683309
DOI
出版ステータスPublished - 2019 5月 24
外部発表はい
イベント34th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2019 - Anaheim, United States
継続期間: 2019 3月 172019 3月 21

出版物シリーズ

名前Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
2019-March

Conference

Conference34th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2019
国/地域United States
CityAnaheim
Period19/3/1719/3/21

ASJC Scopus subject areas

  • 電子工学および電気工学

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