Twisted bit line technique for multi-Mb DRAMS.

Tsutomu Yoshihara, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima

研究成果: Conference contribution

24 引用 (Scopus)

抜粋

The authors propose and demonstrate bitline architecture to eliminate the noise and also overcome the scaling problem of future dynamic random-access memories (DRAMs). Twisted bit line (TBL) techniques which cancel the interbitline coupling noise and improve the signal are described. The interpair coupling noise in the TBL configurations is equally coupled to adjacent paired bitlines and cancelled in the differential sensing operation. In the modified TBL case, the intrapair coupling noise is also eliminated and the signal is improved twice as much as in the TBL case. Thus, in the modified TBL, the bitline-bitline coupling capacitance does not cause coupling noise, but only increases the total bitline capacitance. To demonstrate the effects of the TBL methods, a TBL structure is implemented on a 1-Mb DRAM without layout constraints.

元の言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
出版者Publ by IEEE
ページ238-239
ページ数2
31
出版物ステータスPublished - 1988
外部発表Yes

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Yoshihara, T., Hidaka, H., Matsuda, Y., & Fujishima, K. (1988). Twisted bit line technique for multi-Mb DRAMS.Digest of Technical Papers - IEEE International Solid-State Circuits Conference (巻 31, pp. 238-239). Publ by IEEE.