Twisted bit line technique for multi-Mb DRAMS.

Tsutomu Yoshihara*, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima


研究成果: Conference contribution

24 被引用数 (Scopus)


The authors propose and demonstrate bitline architecture to eliminate the noise and also overcome the scaling problem of future dynamic random-access memories (DRAMs). Twisted bit line (TBL) techniques which cancel the interbitline coupling noise and improve the signal are described. The interpair coupling noise in the TBL configurations is equally coupled to adjacent paired bitlines and cancelled in the differential sensing operation. In the modified TBL case, the intrapair coupling noise is also eliminated and the signal is improved twice as much as in the TBL case. Thus, in the modified TBL, the bitline-bitline coupling capacitance does not cause coupling noise, but only increases the total bitline capacitance. To demonstrate the effects of the TBL methods, a TBL structure is implemented on a 1-Mb DRAM without layout constraints.

ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
出版社Publ by IEEE
出版ステータスPublished - 1988

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学


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