Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Yuuichi Hirano*, Takashi Ipposhi, Dang Hai Thai, Toshiaki Iwamatsu, Tatsuhiko Ikeda, Mikio Tsujiuchi, Shigeto Maegawa, Masahide Inuishi, Yuzuru Ohji

*この研究の対応する著者

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.

本文言語English
ページ60-64
ページ数5
出版ステータスPublished - 2004
外部発表はい
イベントDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium - Honolulu, HI, United States
継続期間: 2004 10 32004 10 8

Other

OtherDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium
国/地域United States
CityHonolulu, HI
Period04/10/304/10/8

ASJC Scopus subject areas

  • 工学(全般)

フィンガープリント

「Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル