Ultra low power QC-LDPC decoder with high parallelism

Ying Cui; Xiao Peng; Zhixiang Chen; Xiongxin Zhao; Yichao Lu; Dajiang Zhou; Satoshi Goto

doi:10.1109/SOCC.2011.6085136

Ultra low power QC-LDPC decoder with high parallelism

Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.

本文言語	English
ホスト出版物のタイトル	International System on Chip Conference
ページ	142-145
ページ数	4
DOI	https://doi.org/10.1109/SOCC.2011.6085136
出版ステータス	Published - 2011
イベント	24th IEEE International System on Chip Conference, SOCC 2011 - Taipei 継続期間: 2011 9 26 → 2011 9 28

Other

Other	24th IEEE International System on Chip Conference, SOCC 2011
City	Taipei
Period	11/9/26 → 11/9/28

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

文献へのアクセス

10.1109/SOCC.2011.6085136

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引用スタイル

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AU - Goto, Satoshi

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AB - This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.

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