抄録
This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.
本文言語 | English |
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ホスト出版物のタイトル | International System on Chip Conference |
ページ | 142-145 |
ページ数 | 4 |
DOI | |
出版ステータス | Published - 2011 |
イベント | 24th IEEE International System on Chip Conference, SOCC 2011 - Taipei 継続期間: 2011 9月 26 → 2011 9月 28 |
Other
Other | 24th IEEE International System on Chip Conference, SOCC 2011 |
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City | Taipei |
Period | 11/9/26 → 11/9/28 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 制御およびシステム工学
- 電子工学および電気工学