Ultra low power QC-LDPC decoder with high parallelism

Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    6 引用 （Scopus）

    抜粋

    This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.

    元の言語English
    ホスト出版物のタイトルInternational System on Chip Conference
    ページ142-145
    ページ数4
    DOI
    出版物ステータスPublished - 2011
    イベント24th IEEE International System on Chip Conference, SOCC 2011 - Taipei
    継続期間: 2011 9 26 → 2011 9 28

    Other

    Other24th IEEE International System on Chip Conference, SOCC 2011
    市Taipei
    期間11/9/26 → 11/9/28

      フィンガープリント

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Control and Systems Engineering
    • Electrical and Electronic Engineering

    これを引用

    Cui, Y., Peng, X., Chen, Z., Zhao, X., Lu, Y., Zhou, D., & Goto, S. (2011). Ultra low power QC-LDPC decoder with high parallelism. ： International System on Chip Conference (pp. 142-145). [6085136] https://doi.org/10.1109/SOCC.2011.6085136

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