Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

Akio Shima, Yun Wang, Somit Talwar, Atsushi Hiraiwa

研究成果: Conference contribution

49 被引用数 (Scopus)

抄録

We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

本文言語English
ホスト出版物のタイトルDigest of Technical Papers - Symposium on VLSI Technology
ページ174-175
ページ数2
出版ステータスPublished - 2004
外部発表はい
イベント2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
継続期間: 2004 6 152004 6 17

Other

Other2004 Symposium on VLSI Technology - Digest of Technical Papers
国/地域United States
CityHonolulu, HI
Period04/6/1504/6/17

ASJC Scopus subject areas

  • 電子工学および電気工学

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