Ultra-shallow junction formation by non-melt laser spike annealing and its application to complementary metal oxide semiconductor devices in 65-nm node

Akio Shima, Atsushi Hiraiwa

研究成果: Article査読

42 被引用数 (Scopus)

抄録

We activated source/drain junctions of complementary metal oxide semiconductor (CMOS) by simply replacing rapid thermal annealing (RTA) in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers, unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those formed by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

本文言語English
ページ(範囲)5708-5715
ページ数8
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
45
7
DOI
出版ステータスPublished - 2006 7 7
外部発表はい

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

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