Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder

Shihao Wang, Dajiang Zhou, Jianbin Zhou, Takeshi Yoshimura, Satoshi Goto

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

This paper presents a VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder. PDec in HEVC is deemed as a highly algorithm-irregular module, which is also challenged by high throughput requirement for UHDTV. To solve these problems, four schemes are proposed. Firstly, the work unifies MV and BS parameter decoders to share on-chip memory and simplify the control logic. Secondly, we propose the CU-adaptive pipeline scheme to efficiently reduce the implementation complexity. Thirdly, on-chip memory is organized to meet the high throughput requirement for spatial neighboring fetching. Finally, optimizations on irregular MV algorithm are adopted for 43.2k area reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support 7680x4320@60fps realtime decoding at 249MHz in the worst case.

本文言語English
ホスト出版物のタイトルLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
出版社Springer Verlag
ページ74-83
ページ数10
8879
ISBN(印刷版)9783319131672
出版ステータスPublished - 2014
イベント15th Pacific-Rim Conference on Multimedia, PCM 2014 - Kuching
継続期間: 2014 12 12014 12 4

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
8879
ISSN(印刷版)03029743
ISSN(電子版)16113349

Other

Other15th Pacific-Rim Conference on Multimedia, PCM 2014
CityKuching
Period14/12/114/12/4

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 理論的コンピュータサイエンス

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