TY - GEN
T1 - User-friendly compact model of magnetic tunnel junctions for circuit simulation based on switching probability
AU - Liu, Haoyan
AU - Ohsawa, Takashi
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - We propose a new compact MTJ model for circuit simulation which is implemented by Verilog-A and can be easily built in de-facto standard SPICE. The model is based on switching probability of an MTJ with time-varying input current. The transition between the adiabatic precessional model and the thermal activation model is made smooth by using an interpolation function with a technique to predict a switching time from an input current. Simulation results validate that the model is consistent with physical model and effective for MTJ/CMOS hybrid circuit simulation.
AB - We propose a new compact MTJ model for circuit simulation which is implemented by Verilog-A and can be easily built in de-facto standard SPICE. The model is based on switching probability of an MTJ with time-varying input current. The transition between the adiabatic precessional model and the thermal activation model is made smooth by using an interpolation function with a technique to predict a switching time from an input current. Simulation results validate that the model is consistent with physical model and effective for MTJ/CMOS hybrid circuit simulation.
KW - Compact model
KW - Magnetic tunnel junction (MTJ)
KW - Spin transfer torque magnetic random access memory (STT-MRAM)
KW - Verilog-A
UR - http://www.scopus.com/inward/record.url?scp=85068601836&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85068601836&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2019.8741646
DO - 10.1109/VLSI-DAT.2019.8741646
M3 - Conference contribution
AN - SCOPUS:85068601836
T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Y2 - 22 April 2019 through 25 April 2019
ER -