VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song*, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

A 1-D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18μm 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25°C), a clock frequency of 266MHz can be achieved.

本文言語English
ホスト出版物のタイトル2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
ページ89-92
ページ数4
DOI
出版ステータスPublished - 2007 10 1
イベント2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan, Province of China
継続期間: 2007 4 262007 4 28

出版物シリーズ

名前2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
国/地域Taiwan, Province of China
CityHsinchu
Period07/4/2607/4/28

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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