VLSI architecture of HEVC intra prediction for 8K UHDTV applications

Jianbin Zhou, Dajiang Zhou, Heming Sun, Satoshi Goto

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

This paper presents an efficient VLSI architecture of intra prediction for 8K×4K HEVC decoder. It supports all 35 intra prediction modes and prediction sizes ranging from 4×4 to 64×64. This works proposed a Cyclic SRAM Banks based Parallel Reference Sample Fetching (CSB-PRSF), which guarantees enough reference samples for prediction and reduces the number of registers used for storing reference samples. To guarantee high throughput, 16 pixels are predicted by 4×4 Block Based Pipelining, and dependency between neighboring blocks is eliminated by Hybrid Data Forwarding and Block Reordering. This architecture is synthesized using 90nm technology and the maximum working frequency is 469 MHz, with 72.1K gates area. Running at 397MHz, the architecture can support 4320p@120fps HEVC intra decoding, with full modes and full sizes.

本文言語English
ホスト出版物のタイトル2014 IEEE International Conference on Image Processing, ICIP 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1273-1277
ページ数5
ISBN(電子版)9781479957514
DOI
出版ステータスPublished - 2014 1 28

出版物シリーズ

名前2014 IEEE International Conference on Image Processing, ICIP 2014

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition

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