VLSI friendly computation reduction scheme in H.264/AVC motion estimation

Yiqing Huang, Satoshi Goto, Takeshi Ikenaga

研究成果: Conference contribution

抄録

In H.264/AVC standard, motion estimation (ME) can be executed on multiple reference frame (MRF) to improve the coding performance. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. So, IME is arranged in a single stage, which deteriorates the efficiency of many fast ME algorithms. This paper provides a VLSI friendly complexity reduction solution for ME procedure. Firstly, the proposed algorithm examines the pixel difference of current macroblock (MB) and adjust the available reference frame number. Secondly, it executes matching analysis to detect MB with static feature and early terminate the IME process. Thirdly, based on motion feature analysis result, the search range for non static MB is also adjusted and redundant search positions are eliminated. Compared with full search algorithm, the proposed fast ME algorithm can reduce 47.91% to 91.88% ME time with negligible video quality degradation. Furthermore, the algorithm can also be combined with other fast block matching process and friendly to hardwired encoder.

本文言語English
ホスト出版物のタイトル2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
ページ844-847
ページ数4
DOI
出版ステータスPublished - 2008 9 24
イベント2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
継続期間: 2008 5 182008 5 21

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷版)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period08/5/1808/5/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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