Power optimization has become a significant issue when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective.
|ホスト出版物のタイトル||Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|
|出版ステータス||Published - 2009|
|イベント||19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA|
継続期間: 2009 5 10 → 2009 5 12
|Other||19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09|
|Period||09/5/10 → 09/5/12|
ASJC Scopus subject areas