Voltage island-driven power optimization for application specific network-on-chip design

Kan Wang, Sheqin Dong, Satoshi Goto

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

本文言語English
ホスト出版物のタイトルProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
ページ171-176
ページ数6
DOI
出版ステータスPublished - 2012
イベント22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT
継続期間: 2012 5 32012 5 4

Other

Other22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
CitySalt Lake City, UT
Period12/5/312/5/4

ASJC Scopus subject areas

  • Engineering(all)

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