Waiting false path analysis of sequential logic circuits for performance optimization

Kazuhiro Nakamura*, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe

*この研究の対応する著者

研究成果: Conference article査読

13 被引用数 (Scopus)

抄録

This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.

本文言語English
ページ(範囲)392-395
ページ数4
ジャーナルIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
DOI
出版ステータスPublished - 1998
外部発表はい
イベントProceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD - San Jose, CA, USA
継続期間: 1998 11 81998 11 12

ASJC Scopus subject areas

  • ソフトウェア
  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計

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