Word error control algorithm through multi-reading for NAND flash memories

This paper presents one error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70% error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1-bit/cell or multi-bits/cell memories.